Workshop Proceedings are Published by the IEEE Computer Society Press

Barcelona, Spain, March 7, 2008; in conjunction with CISIS'08





- The improvement of the processor performance by increasing the clock rate has reached its technological limits. Increasing the number of processor cores rather than clock rate can give better performance and reduce problems like energy consumption, heat dissipation and design complexity. We are witnessing the emergence of multi-core processors in all markets from laptops and game consoles to servers and supercomputers.

Topics of Interest

- The topics of the workshop include but are not limited to:
  • multi-core architectures
  • interconnection networks
  • multi-core embedded systems
  • programming languages and models
  • algorithms for multi-core computing systems
  • applications for multi-core systems
  • performance modeling and evaluation of multi-core systems
  • design space exploration
  • resource usage optimization
  • tool-support for multi-core systems
  • compilers, runtime and operating systems

Submission Guidelines

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- The papers should be prepared using the IEEE CS format, and no longer than 6 pages. Submitted papers will be carefully evaluated based on originality, significance to workshop topics, technical soundness, and presentation quality.
- Submission of the paper implies that should the paper be accepted, at least one of the authors will register and present the paper at the workshop. Proceedings of the workshop will be published by IEEE Computer Society Press. The best papers presented at the workshop will be selected for publication in an international journal.
- The papers should be submitted electronically via CISIS'08 website.

Important Dates

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- Submission: CLOSED
- Notification: December 10, 2007
- Registration: December 20, 2007
- Final version of the paper: January 2, 2008
- Workshop: March 7, 2008

Keynote Address

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TITLE: Petascale Computing for Large-Scale Graph Problems
(Presentation slides as PDF; Photos: 1, 2)
SPEAKER: Prof. David A. Bader
Head of the Sony-Toshiba-IBM center of competence for the Cell BE processor.
Georgia Institute of Technology, USA

Workshop Co-chairs

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- Leonard Barolli, Fukuoka Institute of Technology, Japan
- Sabri Pllana, University of Vienna, Austria
- Fatos Xhafa, Polytechnic University of Catalonia, Spain

Program Committee

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- David A. Bader, Georgia Institute of Technology, USA
- Leonard Barolli, Fukuoka Institute of Technology, Japan
- Siegfried Benkner, University of Vienna, Austria
- Luca Benini, University of Bologna, Italy
- François Bodin, IRISA, University of Rennes, France
- Rajkumar Buyya, University of Melbourne, Australia
- Michel Cosnard, INRIA, France
- Nathalie Drach, University of Paris VI - Pierre & Marie Curie, France
- Michael Gschwind, IBM T.J. Watson Research Center, USA
- Eleni Karatza, Aristotle University of Thessaloniki, Greece
- Michael McCool, University of Waterloo, and RapidMind Inc., Canada
- Pierre Michaud, IRISA/INRIA, France
- Bernd Mohr, Research Centre Jülich, Germany
- Lasse Natvig, Norwegian University of Science and Technology, Norway
- Mohamed Ould-Khaoua, Sultan Qaboos University, Oman, and University of Glasgow, UK
- Sabri Pllana, University of Vienna, Austria
- Vivek Sarkar, Rice University, USA
- Jie Tao, University of Karlsruhe, Germany
- Jesper Larsson Träff, C&C Research labs, NEC Europe Ltd, Germany
- Manolis Vavalis, CERETETH, Greece
- Brian Vinter, University of Copenhagen, Denmark
- Roland Wismüller, University of Siegen, Germany
- Fatos Xhafa, Polytechnic University of Catalonia, Spain
- Hans Zima, University of Vienna, Austria, and JPL/Caltech, USA
Contact Person

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- Sabri Pllana
University of Vienna, Austria
T. +43 1 4277 39411
F. +43 1 4277 9394
E. pllana [at]


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- The workshop registration will be performed via CISIS'08 website.


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- The workshop will be organized in conjunction with CISIS'08, Polytechnic University of Catalonia (UPC), Barcelona, Spain, March 4 - 7, 2008.

| IEEE Computer Society | CISIS'08 |