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CALL FOR PAPERS |
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Context |
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The
improvement of the processor performance by increasing the clock rate
has reached its technological limits. Increasing the number of
processor cores rather than clock rate can give better performance and
reduce problems like energy consumption, heat dissipation and design
complexity. We are witnessing the emergence of multi-core processors in
all markets from laptops and game consoles to servers and
supercomputers. |
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Topics
of Interest |
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topics of the workshop include but are not limited to: |
- :: multi-core architectures
- :: interconnection networks
- :: multi-core embedded systems
- :: programming languages and models
- :: algorithms for multi-core computing systems
- :: applications for multi-core systems
- :: performance modeling and evaluation of multi-core
systems
- :: design space exploration
- :: resource usage optimization
- :: tool-support for multi-core systems
- :: compilers, runtime and operating systems
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Submission Guidelines |
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| - The
papers should be prepared using the
IEEE CS format,
and no longer than 6 pages. Submitted papers will be carefully
evaluated based on originality, significance to workshop topics,
technical soundness, and presentation quality. |
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Submission of the paper implies that should the paper be accepted, at
least one of the authors will register and present the paper at the
workshop. Proceedings of the workshop will be published by IEEE
Computer Society Press. The best papers presented at the workshop will
be selected for publication in an international journal. |
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papers should be
submitted electronically via
CISIS'09 website. |
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Important Dates |
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Submission: CLOSED (October 17, 2008) |
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Notification: November 21, 2008 |
| - Final
version of the paper: December 15, 2008 |
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Workshop: March 16, 2009 |
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Workshop Co-chairs |
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Leonard Barolli, Fukuoka Institute of Technology,
Japan |
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Sabri
Pllana, University of Vienna, Austria |
| - Fatos
Xhafa, Polytechnic University of Catalonia, Spain |
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Program Committee |
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Siegfried Benkner, University of Vienna, Austria |
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François Bodin, CAPS Entreprise, France |
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Martti Forsell, VTT, Finland |
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Michael Gschwind, IBM T.J. Watson Research Center, USA |
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Eleni Karatza, Aristotle University of Thessaloniki, Greece |
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Christoph Kessler, Linköping University, Sweden |
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Keqiu Li, Dalian University of Technology, China |
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Pierre Michaud, IRISA/INRIA, France |
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Bernd Mohr, Research Centre Jülich, Germany |
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Lasse Natvig, Norwegian University of Science and Technology, Norway |
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Ian Rogers, University of Manchester, UK |
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Mitsuhisa Sato, University of Tsukuba, Japan |
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Dilma M. da Silva, IBM T.J. Watson Research Center, USA |
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Leonel Sousa, Technical University of Lisbon, Portugal |
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Jie Tao, University of Karlsruhe, Germany |
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Osamu Tatebe, University of Tsukuba, Japan |
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Walter F. Tichy, University of Karlsruhe, Germany |
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Jesper
Larsson Träff, NEC Laboratories Europe, NEC Europe Ltd, Germany |
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Roland Wismüller, University of Siegen, Germany |
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Contact Person |
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Sabri Pllana |
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University of
Vienna, Austria |
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T. +43 1 4277
39411 |
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F. +43 1 4277
9394 |
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E. pllana [at] par.univie.ac.at |
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<http://www.par.univie.ac.at/~pllana/> |
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Registration |
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| The
workshop registration will be performed via
CISIS'09 website. |
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